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BLOG POSTS
UberDDR4: The Open-Source DDR4 Controller - Post #19
Back in 2023 I released UberDDR3, my open-source DDR3 controller. Three years later, the successor is now here: UberDDR4, the open-source DDR4 controller. This blog post walks through the controller, the PHY, the prober, and the verification flow behind it. And a spoiler for the end: the project I always wanted to do with UberDDR3 but never could, which is UberDDR4 + LiteX + VexRiscv booting Linux on an UltraScale+ FPGA board :) Table of Contents I. Introduction II. Controlle
Angelo Jacobo
8 hours ago10 min read
Pushing UberDDR3 Frequency Through RTL Cleanup - Post #18
A step-by-step walkthrough of pushing UberDDR3 from 90 MHz to 132 MHz using RTL cleanup and the OpenXC7 open-source FPGA flow.
Angelo Jacobo
Feb 138 min read
FPGA Builds Without Local Toolchains: An Intro to CaaS - Post #17
If you’ve been curious about open-source FPGA flows but felt blocked by setup complexity, CaaS makes it simple for you,
Angelo Jacobo
Jan 226 min read
How UberDDR3 Stays Stable: GoCD-Powered CI for Serious Hardware - Post #16
Read through how UberDDR3 uses GoCD for its CI pipeline: from lint to full hardware build!
Angelo Jacobo
Jun 4, 20259 min read
UberDDR3 on Lattice ECP5: Expanding FPGA Support - Post #15
UberDDR3 now running on Lattice ECP5!
Angelo Jacobo
May 2, 20259 min read
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